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The circuit shown in the drawings is a high speed serializer of 8 bits (1 byte) with application to a data transmission scheme which improves the machine Input/Output (I/O) pin performance trade-off.
English (United States)
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Byte Serialization With "T" Master Slave Register and Cascode Circuit
The circuit shown in the drawings is a high speed serializer of 8 bits (1 byte)
with application to a data transmission scheme which improves the machine
Input/Output (I/O) pin performance trade-off.
This circuit comprises two parts: a multiplexer (Fig. 2) designed with cascode
current switches, and a clock frequency divider by 2 and 4 (Fig. 3) providing
gating pulses to the multiplexer.
The gating pulse generator is a divider by 2 and 4 comprising two "T" Master
Slave registers in series. The second register has its inputs connected to the two
outputs of the first register.
The "T" Master Slave has been chosen as its functionality is independent of
the cycle and the duration time of the clock pulses. Furthermore, it provides
gating pulses which are either synchronized on up- or down-going transitions of
the clock pulse, which allows the number of frequency divisions for serializing 8
bits to be reduced.
As shown on Fig. 1, the master or the slave is an elementary cell of two
coupled transistors T2, T3 or T6, T7 with two resistors R1, R2 or R3, R4
connected to the collectors of these transistors.
Only one cell maintains the state of the register as the clock allows the
current J2 to be steered through one of the two transistors T9 and T10.
Transistors T1, T4 or T5, T8 predetermine the node voltages of the unselected
cell opposite the selected one. At the clock transition when current appears in...