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This chip has one bit line and/or one word line inplace-spare along with appropriate logic to allow substitution for faults at manufacture for yield enhancement or any other time for field repairs.
English (United States)
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Fault-Tolerant Memory Chip Architecture for Yield Enhancement and Field
This chip has one bit line and/or one word line inplace-spare along with
appropriate logic to allow substitution for faults at manufacture for yield
enhancement or any other time for field repairs.
The spare consists of a word line 10 and bit line 12, which are selected by a
select control bit S generated by X and Y bit by bit compare circuits 14 and 16,
respectively. The X or Y address to be replaced is preset in the X or Y shift
register 18 or 12, respectively. The contents of the shift registers and the
address bits are compared by the bit by bit compare circuits l4 and l6 to select
the spare and deselect the X and Y rows in the main array 22.
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