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Asynchronous Gated Ternary J-K Flip-Flop Disclosure Number: IPCOM000046272D
Original Publication Date: 1983-Jun-01
Included in the Prior Art Database: 2005-Feb-07

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Maholick, AW [+details]


A ternary J-K flip-flop is a multistate circuit having two inputs. Each input, when energized, sets the flip-flop to a corresponding stable output state which will be held after the energization is removed. If both inputs are simultaneously energized, the flip-flop will change from its current state, q, to the next state, Q, in accordance with the equation: (Image Omitted)