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This hardware enhances the throughput of any test system and provides a self-adjusting feature for capturing the first and last failing addresses.
English (United States)
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Optimized Data Transfer Function for Memory Cell Map Buffers
This hardware enhances the throughput of any test system and provides a
self-adjusting feature for capturing the first and last failing addresses.
The first failing address of the device under test (DUT) is loaded in both the S
register and the L Register. Any other failing address is compared in the S
comparator for S smaller than A (SOA) and the L comparator for L greater than A
(LJA). If these conditions are not true, the new failing address A is loaded in the
corresponding register - either the S register (S Reg) or the L Register (L Reg).
After a multitude of test sequences with map overlaps on the DUT, the S
Register will contain the first failing address for all tests while the L Register will
contain the last failing address of the DUT for all tests. These two words are
transfered to the CPU, and the Data Block transfer is confined between those
In the transfer to CPU mode there are two options depending on the tester to
CPU interface and in the shared memory interface, the S and L values transfer
sufficient information for initiation and completion of the transfer.
PG and PNP in the figure represent Pattern Generator and Part Number
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