Selective GLOBAL Clock Control for a Multi-Processor SYSTEM
Original Publication Date: 1983-Jul-01
Included in the Prior Art Database: 2005-Feb-07
Activation l) A Central Processor Logic Support System (LSS) receiving a 'modulo 9' (GLOBAL) interrupt. 2) Receiving a hard interrupt from a functional element that has its clock-stopping control masked for continuous operation. 3) The count going to zero during a stop on count/error (SOCE) command to a functional element with LSS ID register bit 9 on. This will generate a global hard stop line which is sent to the System Controller-LSS for control. 4) START, STOP, or SOCE command to a System Controller-LSS with an ID Register Bit (10-15) specification of '100111'B, '101000'B, or '101001'B (LOCAL SYSTEM, REMOTE SYSTEM, TOTAL SYSTEM).