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Parallel Random Test Generation Disclosure Number: IPCOM000046477D
Original Publication Date: 1983-Jul-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 54K

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This apparatus generates multiple tests in parallel.

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Parallel Random Test Generation

This apparatus generates multiple tests in parallel.

Latch circuits 12 embodied in semiconductor circuitry 14 are shift register latches (SRLs) formed by a serial path 16 to permit the entry and removal of data in series for testing purposes. These latches can be connected together to form a Y-1 linear feedback shift register (LFSR), as shown in Fig. 2, to generate PN sequences Y of length 2Y-1, illustrated in Fig. 3. PN sequences generated by the LFSR on one chip can be used to generate the PN sequences for an adjacent chip, as shown in Fig. 1.


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