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Improved Signature Test for VLSI Circuits

IP.com Disclosure Number: IPCOM000046557D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Carter, JL [+details]

Abstract

When testing VLSI (very large-scale integration) circuits using a signature testing technique, a circuit whose responses are incorrect could still have the same signature as a good circuit. The method described herein reduces the chance of this happening. Several methods for testing VLSI chips can be classified as signature methods. Such a method applies a number of test patterns to the inputs of the circuit and accumulates the outputs of the circuit by some data compression device. After all the test patterns have been applied, the signature - the final contents of the accumulator - is examined to see if it agrees with the signature produced by a good chip. Signature testing methods have several advantages over conventional testing in which each output pattern is examined individually.