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Effective Master-Slave Latch Combination

IP.com Disclosure Number: IPCOM000046568D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
St. Clair, JC [+details]

Abstract

For an effective use of dual data port-dual clock master latches M paired with simple slave latches S, being in operation testable in accordance with level sensitive scan design (LSSD) rules, each master latch M is driven by a unique gated clock C. For loading the slave latches S, first all their master latches M are loaded and then all slave latches S are gated together, copying the data in the master latches M into the slave latches S. After that, the master latches M are loaded individually with their appropriate data. So each used latch stores one data bit, and the circuit can be scanned during testing.