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Pattern Generator for Memory Test System

IP.com Disclosure Number: IPCOM000046625D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Megivern, CF [+details]

Abstract

This is a technique for dynamically generating a memory test pattern. A combined network permits complicated data patterns to be synthesized from simpler ones. As illustrated in the drawing, an address generator provides the address to be tested. Addresses can be provided at random, as for a random-access memory. Alternatively, the address generator can be a simple counter which serially addresses either a serial memory (such as a charge-coupled device memory) or a random-access memory. Each of the data equation units (1, 2, 3) stores a relatively simple test pattern, usually hard wired. For example, data equation unit 1 may provide the generation of all binary "1's" in a column of memory cells in the parallel section of a serial-to-parallel-to-serial memory.