FIFO Buffer Memory Comprising a Random-Access Memory and Two Pointers
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
The FIFO (first-in, first-out) buffer function is more and more required in various digital systems, particularly to interface a synchronous subsystem. The firmware (or software) approach requires program or microprogram execution and thence delay. On the other hand, a battery of shift registers might be implemented to achieve this function, but it is known to be silicon and power consuming. Therefore, herein is proposed a hardwired implementation of a FIFO, which saves both silicon area and power dissipation, on the one hand, and reduces time delay, on the other hand. The FIFO function comprises two pointers and a RAM (random-access memory), which has a latched output (L. RAM). The circuit is shown in Fig. 1.