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Set of SHIFT Registers Formed From a FIFO Buffer Memory

IP.com Disclosure Number: IPCOM000046645D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
D'Hervilly, G De La Salle, C [+details]

Abstract

In digital signal processing it is often desired to have a battery of shift registers working as a buffer or a delay line. Normally this problem may be solved by implementing a series of master slave latches sequentially connected; however, this solution is recognized as requiring much silicon area and dissipates much power. When minimizing both power dissipation and silicon area is a must, the following implementation based on a FIFO (first-in, first-out) buffer memory, such as described in the preceding article, which not only considerably reduces power dissipation and silicon area but also adds flexibility in case of implementing a specially timed buffer. The basic principle of a shift register set is shown in Fig. 1, and the timing is shown in Fig. 2. Information encoded on "N" bits arrives on the IN.BUS at each cycle.