Browse Prior Art Database

Asynchronous Clock Switching Filter

IP.com Disclosure Number: IPCOM000046710D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Bakken, KL Peterson, RA Petz, BR [+details]

Abstract

In many direct-access storage devices (DASD) the interface between device and attachment provides a serial data port and corresponding read and write file clocks. In a level sensitive scan design (LSSD) two non-overlapping clocks must be generated from the file read clock or the file write clock. Depending on the operation required from the DASD device, the file clock used must switch from one to the other within a specified number of cycles (usually 2-3 cycles). A typical clock switching circuit is shown in Fig. 1. The "gate read/write clock" signals, which are externally generated, are used to select between the DASD read and write clocks for clocking the internal LSSD latches. Blocks 4 through 11 are used to produce non-overlapping LSSD clock pulses.