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Fabrication Procedure for Self-Aligned Contacts of MOSFET Integrated Circuits

IP.com Disclosure Number: IPCOM000046741D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Chao, HH Ephrath, LM [+details]

Abstract

A self-aligned contact fabrication method is described wherein after forming polysilicon gate FETs (field-effect transistors) up to the source-drain regrowth point by conventional techniques, a thin insulating layer is deposited that has an etch rate much lower than the etch rate of CVD (chemical vapor deposited) SiO2 with an anisotropic etching process, and which is permeable to hydrogen at a high temperature of 400 to 500ŒC. A thin layer of Si-rich oxide (500 nm) is an example of a material that has these properties when deposited and annealed in an appropriate manner. CVD SiO2 is then deposited and a contact hole pattern is developed in resist. The CVD SiO2 is etched in an etching gas that is selective for SiO2 .