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Card Debug Through Isolation to a Failing Micro Instruction Cycle

IP.com Disclosure Number: IPCOM000046815D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue


Related People

Jones, JF Thatcher, LE Whitting, LE [+details]


A method is described to debug CPU cards to a failing micro-instruction cycle in the event the cards fail the final functional system tests after passing all the previous tests. The method involves observing the main internal bus of the processor ('Proc Bus'). Because of the processor's dependence upon this multi-purpose bus, detecting a failure there results in isolating the problem to a single micro-instruction cycle. Once isolated to this level, the task of finding the failing component is greatly simplified. Some CPUs, such as the IBM Series/1 CPUs, are designed in such a way that the "Proc Bus' is gated to the Series/1 Channel Address Bus via the Storage Address Register (SAR). The SAR is loaded from the "Proc Bus' every micro-instruction cycle until a CPU request to Main Storage Access is decoded.