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Test Pattern Generation for Partitioned Programmable Logic Arrays

IP.com Disclosure Number: IPCOM000046823D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Muhr, JT Patch, FD [+details]

Abstract

Test pattern generation for either single-bit or double-bit partitioned programmable logic arrays (PLAs) has been accomplished in a similar manner to other combinational circuit test pattern generation. The logic combinations of the AND and OR circuits are first broken down into primitives, normal stuck fault generation is performed, and then fault simulation on the primitives is done. This produces a rather large test pattern set which must be stored in the system and transmitted to the tester. The process is time consuming and requires capability to handle the abundance of data. An alternate technique is to randomly select the test patterns. Unfortunately, these methods do not give 100% detection of PLA failures.