System Master Slice for Fast Turnaround Time
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
This is an improved microprocessor and an improved technique for fabricating a microprocessor on a semiconductor master slice. As illustrated in the figure this is a personalizable microprocessor on a single semiconductor chip containing not only the microprocessor unit (MPU) but also the peripheral input/output (PIO), a function execution unit (FEU), and a read-only store (ROS) as well as a random-access memory (RAM). A significant aspect of this arrangement is that the FEU and PIO are formed from programmable logic arrays (PLA) for design flexibility at the personalization level. Another important aspect is that the internal bus is common to all elements of the micro processor on the semiconductor master slice (SMS) so that "add on" items are directly pluggable by means of an external bus connected to the internal bus.