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Four-Phase Signal Generator Using a Balanced Input/Output Driver

IP.com Disclosure Number: IPCOM000046838D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Froment, JC Verhaeghe, M [+details]

Abstract

The circuit shown in the drawing provides a four-pulse signal shifted by f/4 with a zero pulse width skew. The oscillator provides on its first output (+OSC) a first signal and on its second output (-OSC) the complement of the first signal, which is delayed by a delay circuit (DEL). Two clock driver circuits CDM1 and CDM2, each having two inputs IN and IN, provide four output signals 0/1, 0/2, 0/3 and 0/4, each having a f/4 shift with respect to the other, as shown in the figure. Each clock driver circuit comprises a receiver (REC) and a driver (DRV), shown in detail in the figure. The receiver is a emitter-coupled transistor circuit with current source transistor T3, and emitter follower transistors T4 and T5. According to the levels on inputs IN and IN, either one of the transistors T1 and T2 is conducting.