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Sequential Access to Hierarchical Memories

IP.com Disclosure Number: IPCOM000046847D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Najmann, K Schmidt, F Straehle, W [+details]

Abstract

Known memory chips are generally not hierarchically organized but are addressed by row and column selection. For this purpose, the data of a row are read into associated sense latches. Subsequently, one of the sense latches is selected and read. Memory chips may additionally comprise integrated buffers, or such buffers may cooperate with one or several chips. If a particular address is accessed, the buffer is loaded by the larger memory and subsequently sequentially read or overwritten by controlling the selected buffer address through an associated bus. In a write cycle, the data are written in parallel from the buffer to the larger and slower memory. The new concept is such that a memory chip is provided with an additional integrated three-stage binary counter, as illustrated.