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Browse Prior Art Database

High Performance Multiple Pu-Shared Scientific Processor Concept

IP.com Disclosure Number: IPCOM000046857D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Blum, A [+details]

Abstract

In multiple processing unit (PU) systems, the PUs may be connected (a) to a shared or non-shared memory subunit through a common single system bus, controlled by a bus arbiter subunit, or (b) directly to a shared memory (dotted lines, Fig. 1). For scientific applications, a floating-point unit (FPU) is provided which is time-shared by more than one PU of the multiprocessor system. It is assumed that the FPU supplies multiple data and status sets (floating-point registers, etc.). The FPU provides sophisticated functions for the fast execution of floating-point instructions. The data and the control and status information for the floating-point operations are transferred to the FPU by the PU which retrieves the result and status data from the FPU after execution of the floating-point instructions.