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Self-Test Checkpoint Hardware

IP.com Disclosure Number: IPCOM000046877D
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Calvin, DA [+details]

Abstract

This random self-test configuration provides immediate pass/fail indication without the need to scan out the signature and compare. At the beginning of the test, the Multiple Input Signature Register (MISR) 10 is loaded so that it will contain all zeros after the test. Due to the MISR's linear and Exclusive-ORing functions, the same signature arrived at by loading zeros and running a number of random tests will, if loaded as the seed at the start of test, cause the MISR output to be all zeros after the same number of tests is run. Thus, the test signature is loaded into the MISR, the test is run, and the MISR contains all zeros now. Each of the MISR latches is connected to the input of an OR circuit - such that any 1 will make the OR. Now, the only time the OR output is zero is when all the MISR stages are zero.