Interface Bus Configuration
Original Publication Date: 1983-Aug-01
Included in the Prior Art Database: 2005-Feb-07
A problem encountered when interconnecting high and low speed unbuffered devices together on a common bus is that the bus cycle is typically set by the requirements of the high speed device. The proposed invention reduces the impact of the high speed device on the bus cycle time. The bus cycle is determined by the processor and may be variable in length, dependent on the service being addressed and the amount of concurrency with other devices on the bus. The new interface bus configuration, as illustrated in the drawing, supports two types of data transfer cycles. The first type under direct program control (DPC) is used to load commands/parameters to the devices or to sense their status, and the second type by direct memory access (DMA) is used only to transfer data directly between the memory and the devices.