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Disable Circuit for RAM Refresh Timer Disclosure Number: IPCOM000047009D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07

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Norgren, KS [+details]


This article describes a circuit for disabling the internal refresh timer of a dynamic random-access memory (RAM) controller without using a special purpose "disable timer" program pin. Dynamic RAM requires periodic refresh cycles to retain stored data. These refresh cycles are normally requested by a timer internal to a RAM controller. Since, however, memory access is prohibited during the refresh cycle, the forced refresh costs the system some part of its total bandwidth. To counteract this factor, most RAM controllers allow an external refresh request when the system is not otherwise using the memory. The external refresh request is applied through a special program pin and resets the timer which then continues to request refresh cycles at its normal rate.