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# Ring Multiplier Circuit

IP.com Disclosure Number: IPCOM000047069D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 2 page(s) / 37K

IBM

## Related People

Stoppa, P: AUTHOR

## Abstract

This article describes a ring multiplier circuit which is used to monitor VLSI chip manufacturing. The circuit comprises a 2-bit x 2-bit multiplier made of four identical cells. The logical operations performed in one cell are: The multiplicand bits A1A0 are 11, and the most significant bit B1 of the multiplier is 1. The least significant bit B0 is connected to the second-order bit R1 of the four-bit result. To force the least significant bit B0 to 0 at the beginning of the operation, R1 is ANDed with a reset signal in gate A. When the reset signal equals 1, the oscillations of the four bits R3-R0 begin. The oscillation period is four times the average delay of one cell plus two times the average delay of gate A. The probing of any one of the result bits supplies information about the average circuit delay.

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Ring Multiplier Circuit

This article describes a ring multiplier circuit which is used to monitor VLSI chip manufacturing. The circuit comprises a 2-bit x 2-bit multiplier made of four identical cells. The logical operations performed in one cell are: The multiplicand bits A1A0 are 11, and the most significant bit B1 of the multiplier is 1. The least significant bit B0 is connected to the second-order bit R1 of the four-bit result. To force the least significant bit B0 to 0 at the beginning of the operation, R1 is ANDed with a reset signal in gate A. When the reset signal equals 1, the oscillations of the four bits R3-R0 begin. The oscillation period is four times the average delay of one cell plus two times the average delay of gate A. The probing of any one of the result bits supplies information about the average circuit delay. Furthermore, by testing the two high-order bits R3 R2 the delay in generating the carry Co on the partial product Po of a basic cell of the multiplier is measured. This electrical arrangement of the multiplier cells may be embodied in the test sites which are fabricated with the actual circuits or in the kerf portions assigned to the test operations. It allows the operating speed of one cell to be measured. Each variation of the speed average measured in a circuit batch indicates a drift in the semiconductor circuit manufacturing process.

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