Timing Recovery Circuit
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07
In digital telephone systems where signals are transmitted in bursts of about 10 bits from line attachment modules, the subscriber station needs to recover bit timing for further handling of the digital signals. A known technique for timing recovery is based on start-stop operation. The first bit (start bit) received by the station resets a counter which is driven by a fixed frequency clock. The counter drives a decoder DEC which drives a sampling gate, for the detection of subsequent bits, with the proper phase relative to start bit transition (start pulse). The disadvantage of this technique is that timing error made on the start pulse adds to the timing error of each subsequent bit. Therefore, a costly high speed counter is necessary, typically running at 4 MHz.