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Selectable Circuit Master Slice

IP.com Disclosure Number: IPCOM000047085D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07

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Hoover, RA [+details]


Fig. 1 illustrates a three-input NOR with a 3X current capability employing the selectable circuit master slice invention, and Fig. 2 is the circuit schematic diagram for the NOR circuit. The chip image for the selectable circuit master slice comprises horizontal regions, each such region consisting of two parts: a lower portion consisting of the spaced, mutually parallel rows of horizontal diffusion segments Dij (employing the matrix notation shown in Fig. 1) which serve to form the active FET logic devices, and an upper portion consisting of the spaced pairs of diffusions Ldj (drain diffusions) and Lsj (source diffusions) which will form self-biased load devices which are juxtaposed with the corresponding active FET devices in the lower portion. The three-input NOR circuit with a 3X current drive capability of Fig.