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High Speed Testable Clock Pulse Generator Circuit

IP.com Disclosure Number: IPCOM000047094D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Greenberg, R [+details]

Abstract

This circuit provides output pulses from each of pre-drive blocks E1 to EN and F1 to FN at half the frequency of input oscillator O driving latch L, with each of the blocks of the circuit beyond the latch having no more than two inputs each to provide a high speed circuit and with -SCAN C and -SCAN B inputs utilizing parts of the circuit for testing purposes. Latch L is a latch of the "D" type well known in the art and has the D and CLK input terminals respectively for data and controlling clock pulses. Latch L also has output terminals Q and Q. Oscillator O is connected with the CLK terminal of latch L.