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# Averaging Positions

IP.com Disclosure Number: IPCOM000047139D
Original Publication Date: 1983-Sep-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 5 page(s) / 49K

IBM

## Related People

Otten, RH: AUTHOR

## Abstract

1. Introduction Usually, when a system to be integrated enters the stage of its physical design, its inherent structure is obscured or lost, because of many - often automatic - minimizations, assignments, and decompositions. In order to recover or to derive a structure suitable for layout design partitioning on a module-by-module basis, pairwise interchange, force vector formulations, and min-cut algorithms have been introduced. These methods are time-consuming, and their results not often satisfactory. Though the ultimate solution clearly lies in a better integration of design tasks, we still have to try to invent methods that can handle large amounts of unstructured data in a global way, i.e., by considering the whole interconnection structure. 2. An Example We first consider the one-dimensional module array style.

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Averaging Positions

1. Introduction Usually, when a system to be integrated enters the stage of its physical design, its inherent structure is obscured or lost, because of many - often automatic - minimizations, assignments, and decompositions. In order to recover or to derive a structure suitable for layout design partitioning on a module-by-module basis, pairwise interchange, force vector formulations, and min-cut algorithms have been introduced. These methods are time-consuming, and their results not often satisfactory.

Though the ultimate solution clearly lies in a better integration of design tasks, we still have to try to invent methods that can handle large amounts of unstructured data in a global way, i.e., by considering the whole interconnection structure. 2. An Example We first consider the one-dimensional module array style. It applies to technologies with a module layer and a wiring layer electrically insulated from each other everywhere except for the contact areas which form the pins of the modules. In the module layer the modules form mutually disjoint domains satisfying a spacing rule specifying a minimum distance between points from different domains. There are no other restrictions on the position of the pins of a module beside containment in the respective module domain and spacing rules, center-to-center as well as center-to-domain boundary. Further, the contact areas are subject to rules concerning minimal dimensions.

The nets are realized by regions of conductive material in the wiring layer also satisfying spacing rules similar to those for module domains. A region realizing a net must cover the contact areas of its pins, whereas contact areas not pertaining to its pins must be avoided. Outside the contact areas minimum dimensions apply to cross-sections. The one-dimensional module array style divests the layout problem from all its geometrical detail. It requires the module domains to be strips, all oriented in the same direction, with no limit on its longitudinal dimension. The centers of the contact areas are to be positioned on the center line of their module domain and on perpendicular lines, called tracks. Pins belonging to the same module may not be connected via the wiring layer. The center lines and the tracks are the only relevant entities in one-dimensional module array layouts. Since the modules are represented by parallel center lines in the symbolic layout, we can speak of a module sequence. For each module sequence there exists an assignment of nets to tracks which realizes all the required connections. For each individual circuit the set of modules is fixed, and consequently, so is its size in the direction perpendicular to the module center lines under the actual design rules. Any area-saving strategy must therefore aim at minimizing the number of tracks. Abstractly formulated, the problem is as follows: Given a set of modules M and a netlist (with N being the set of nets a netlist is a biv...