Gated Register Pattern Generator for High Speed RAM Testing
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07
This is a gated register pattern generator for high speed random-access memory (RAM) testing which uses level sensitive scan design (LSSD) scan for high speed array testing and a high speed pattern generator without microcode or pipeline delays and circuit speed limitations, thus replacing present costly test techniques. A high speed RAM test method is shown in the figure. A plurality of registers 10 is loaded via a scan path 11. Each of the registers 10 contains read, write and control data and address information, i.e., a register stack. A multiplexer 12, controlled by a gated oscillator 13, selects the device under test (DUT), addresses, data and control information at high speed without microcode.