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Reducing RAM Requirements for a Row, Column Addressed CRT

IP.com Disclosure Number: IPCOM000047219D
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Stockwell, DA [+details]

Abstract

This article describes an approach to minimizing the amount of RAM required to implement a direct RAM addressing using CRT row and column counts. Use is made of a format control bit to select and gate row and high-order column address bits. Row and column addressing of RAM in a non-intelligent display, which refreshes directly from its refresh RAM buffer without using row buffers, allows easy implementation of the following added functions: row column indicator, cross-hair cursor, windowing, scrolling, etc. However, a very large quantity of RAM may be required, especially in a variable format display. For example, if the format used is 160 characters per row by 50 rows, 14 address lines could be required (8 for columns and 6 for rows).