Performance Selection Method Based on Current Measurement in LSI Chips
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07
LSI logic circuits exhibit a large 'delay multiplier' between nominal performance and worst-case performance. A typical multiplier is 2, although, in general, this is dependent on technology (bipolar, FET, and so forth) and specified control of various process parameters (W/L ratios, threshold mobilities in the case of FETs). Also, the probability density function of delay values for a logic block implies that relatively few cases extend to the 'tail' of the distribution to cause this large delay multiplier. It is well known that there is a high correlation between current and performance. This article describes a simple method of selection based on current measurement in LSI chips that permits discarding the relatively few cases on the tail of the distribution.