Browse Prior Art Database

User-Transparent Fault-Alignment Exclusion Management

IP.com Disclosure Number: IPCOM000047313D
Original Publication Date: 1983-Oct-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Bachman, BE [+details]

Abstract

Double hard faults detected in the same ECC word are misaligned, without removing the memory from user control, by a combination of techniques including double error correction, chip pair swapping and data scrubbing. Single errors are allowed to accumulate, without taking any remedial action, until a double error occurs in the same ECC word. Each ECC word contains bits from respective memory array chips, each chip contributing only one bit to a given ECC word. Without requiring user concurrence (without removing the memory from user control), one of the chips which is contributing a faulty bit to the detected double error is swapped with another chip which is error-free. The swapping is accomplished by memory address permutation.