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Self-Aligned FET Gate Structure and Method

IP.com Disclosure Number: IPCOM000047322D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Ishaq, MH Noble, WP [+details]

Abstract

A field-effect transistor (FET) structure and method for fabricating same are described which provide devices with self-aligned gates, low source/drain resistance with integral wiring capability and low parasitic capacitance to other electrodes including the semiconductor substrate. A field region 10 is formed using any of several methods such as recessed oxide, field shield or planar thick oxide 12 is disposed on a semiconductor substrate 14, and a pattern including opening 16 is defined for active device regions, as indicated in Fig. 1. A silicide or silicide-polysilicon layer 18, doped with an N type dopant, e.g., arsenic, is deposited with an overlaying silicon dioxide layer 20.