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Bit Line Transfer Efficiency Measurements at In-Line Testing

IP.com Disclosure Number: IPCOM000047325D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Warren, MJ [+details]

Abstract

This article describes a method for measuring the approximate transfer efficiency of dynamic memory cells using the DC testers that are used for in-line monitoring and characterization of devices. The charge present in a cell will not charge the bit line to the potential stored in the cell but only to a fraction of that voltage. Thus, the transfer efficiency of a given memory cell is defined as the efficiency with which voltage stored in a storage node can be transferred to a sense amplifier input. The measurement technique published in this article is performed on test sites or with slightly modified array structures. In Fig.