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Memory Cell With Minimized Negative Resistance Effects

IP.com Disclosure Number: IPCOM000047329D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Hargrove, MJ Masenas, CJ [+details]

Abstract

A complementary transistor switch (CTS) memory cell has a layout which minimizes extrinsic resistance of the NPN base region by splitting the base contact between two P+ base diffusions coupled by a Schottky barrier diode contact. This minimization of the extrinsic base resistance decreases the negative dynamic resistance effects of the cell which is necessary for stable operation. The electrical circuit of the cell is shown in Fig. 1. The circuit includes first and second cross-coupled bipolar NPN transistors T1 and T2, respectively, each having a pair of dual emitters, first and second PNP transistors T3 and T4, respectively, and first and second Schottky barrier diodes D1 and D2, respectively. A cross-section of the layout of the half cell, i.e., devices T1, T3 and D1, is illustrated in Fig. 2. As seen in Fig.