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Formation of Sub-Micron Patterns With Negligible Tolerance

IP.com Disclosure Number: IPCOM000047349D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Abbas, SA Magdo, IE [+details]

Abstract

In defining sub-micron features in silicon integrated circuit technology, one normally resorts to the use of electron beam resist exposure machines. However, these machines have certain drawbacks. Among these drawbacks is the large investment required and also the image tolerance which can be a sizable percentage of the nominal width and the throughput limitations. It has already been shown in, for example, U.S. Patent 4,322,883 that with self-aligned metal technology, sub-micron studs and spacings can be obtained with enhanced tolerance (about 10 to 20 nanometers) determined by thermal oxidation or chemical vapor deposition (CVD) tolerances. However, this does not solve the problem of image tolerance on dimensions defined by the studs. These spacings are still determined by the capability of the lithographic tool being used.