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Word Line, Bit Line Address Interchanging to Enhance Memory Fault Tolerance

IP.com Disclosure Number: IPCOM000047355D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Singh, S Singh, VP [+details]

Abstract

By the provision of simple address-swapping logic, to interchange word line and bit line addresses, the fault tolerant capacity of a memory using fault alignment exclusion-inclusion techniques can be significantly increased. In the design of fault tolerant memory using fault alignment exclusion-inclusion techniques, if a chip with a bit line fail aligns with another chip with a word line fail, then the memory produces a memory word with a 2-bit error. If the memory is equipped with SEC/DED code, then through address translation these two chips are misaligned so that the memory word in the reconfigured memory has only a 1-bit error. Such a reconfiguration using address translation alone limits the number of bit line, word line and cell fails which can be dispersed.