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Fault Realignment Through Grouping of Compatible Faulty Memory Chips

IP.com Disclosure Number: IPCOM000047358D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Ryan, PM [+details]

Abstract

Fault tolerance in memories is enhanced by mapping and categorizing faulty memory chips by fault type and then permitting only those chips having compatible faults to contribute bits to the same error-correcting code (ECC) words. One method of fault tolerance in memories is to move (electronically rather than physically) faulty chips so that they do not simultaneously supply data to any one ECC word. Another method is to steer the data from faulty chips so that most of the chips supply ECC words in some small block of addresses and then, by software means, assure that no reference is made to the affected block (address block de-allocation).