The InnovationQ application will be updated on Sunday, May 31st from 10am-noon ET. You may experience brief service interruptions during that time.
Browse Prior Art Database

Distributed Permutation Logic for Fault-Tolerant Memories

IP.com Disclosure Number: IPCOM000047359D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue


Related People

Singh, S Singh, VP [+details]


Address permutation logic facilitates the dispersion of faulty bits throughout a memory in such a way that the number of faults per data word is brought within the error correction capability of the system. It has been found, however, that when the faulty bit dispersion logic itself is distributed throughout the memory system, a few bits of permutation logic at each system level (e.g., chip, module, card and board) provide wider fault coverage than do a large number of bits of centralized permutation logic at one location only (e.g., card). As shown in the figure, address bits arriving at the permutation logic on bus 1 are branched to card bus 2, module bus 3 and chip bus 4. Each of the branched addresses is selectively incremented in a respective adder such as address 5, 6 and 7.