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Power-Down Circuit for Low Power Memory Using Harpnp Cell

IP.com Disclosure Number: IPCOM000047364D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Denis, B Omet, D [+details]

Abstract

The circuit shown in the drawing sets a memory in standby mode when the memory is not in use in order to save up to 40% of the total dissipated power. The power-down circuit is used in a memory wherein decoder circuit drives PNP transistors in a current mirror arrangement for providing the base current of the word drivers. It comprises a TTL interface circuit 1 and an inverter stage comprising transistors TX1 and TX2. The collector of transistor TX2 is connected at node A to the collector of transistor T3, the base of transistor T4 and to resistor R3 in the reference decoder 2. In standby mode, circuit 1 is active when a down level is provided to control input IN.