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Dielectrically Isolated CMOS Structure Fabricated by Reverse Trench Process Disclosure Number: IPCOM000047488D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07

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Lai, FSJ [+details]


This article relates generally to processes for fabricating electrically isolated semiconductor devices and more particularly to a process for fabricating electrically isolated complementary metal-oxide-semiconductor (CMOS) devices to solve the latch-up problem in ==/== devices. (Image Omitted) The latch-up problem in CMOS structures is primarily caused by the depletion region of the n-well or p-well. If the whole well can be surrounded by dielectric materials, the CMOS structure becomes latch-up free. This article shows a process whereby a dielectrically isolated CMOS structure is fabricated using a "reverse trench" process. The process includes the following steps: 1. Referring to Fig.