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Browse Prior Art Database

Cache Coherency Without Line Exclusivity in MP Systems Having Store-In Caches

IP.com Disclosure Number: IPCOM000047502D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Pomerene, JH Puzak, TR Rechtschaffen, RN Sparacio, FJ [+details]

Abstract

By modifying the function of the storage control unit (SCU), a multiprocessor (MP) system having store-in caches is enabled to operate with the same versatility as an MP system having store-through caches, thereby eliminating the requirement for line exclusivity and greatly reducing the occurrence of cross-interrogates. In presently available MP systems having store-in cache organizations, such as the IBM 3081 system, for example, the need for cache coherency requires those lines which are targets of a processor's storage requests (stores) to be held within that processor's cache exclusive of other caches in the system, and such stores must be held off until the targeted lines have been invalidated in all other caches.