Browse Prior Art Database

Split Second-Level Cache

IP.com Disclosure Number: IPCOM000047503D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Pomerene, JH Puzak, TR Rechtschaffen, R Sparacio, FJ [+details]

Abstract

This level-splitting technique enables a new level to be created i memory hierarchy without requiring that it be significantly larger than the next higher level. In current multilevel memory hierarchies, each level is a subset of the next lower level, thereby requiring that the lower level be significantly larger. Such an approach can limit the number of levels. For instance, in a memory hierarchy having three cache levels L1, L2 and L3, wherein L1 stores 64K bits and L2 stores 1M bits, if L2 is required to be a subset of L3, then L3 would require a 2M bit capacity to justify itself. In many cases, this large cache size would be prohibitive. A different approach, therefore, is needed in the design of L2 and L3.