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Burst-Controlled Prefetching to Reduce Finite Cache Penalty

IP.com Disclosure Number: IPCOM000047504D
Original Publication Date: 1983-Nov-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Hoevel, LW Voldman, J [+details]

Abstract

To reduce the finite cache penalty in memory systems having variable-length lines, it is proposed to control the prefetching process in such a way that the shorter lines are prefetched during bursts of cache misses and the longer lines are prefetched during the gaps between bursts. Extensive observations of cache performances show that cache misses generally occur in closely timed clusters, herein termed "bursts", that are separated from each other by relatively long intervals, called "gaps", in which there are no misses or only sparsely occurring ones. In systems which store variable-length lines the performance can be greatly improved by using a known burst detector [*] to control the prefetching scheme so that only short lines are prefetched during bursts and long lines are prefetched during gaps.