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Self-Aligned NPN Transistor Process

IP.com Disclosure Number: IPCOM000047523D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Bergeron, DL Chesebro, DG [+details]

Abstract

A process is provided for the formation of a self-aligned NPN transistor compatible with a shallow junction and a highly doped extrinsic base. The process uses ion implantation and lift-off techniques rather than polysilicon for self-alignment. Additionally, a Schottky barrier diode with a self-aligned guard ring may be fabricated simultaneously. As indicated in Fig. 1, the process includes growing a layer of silicon dioxide 10 on a semiconductor substrate 12 and then depositing a thin layer 14 of silicon nitride on layer 10. A first layer 16 of photoresist is applied over silicon nitride layer 14, and an opening 18 is formed therein for defining the emitter of the NPN transistor. As shown in Fig. 1, the opening 18 is made wider at the bottom than at the top of layer 16 by any known method.