Browse Prior Art Database

Scan String Loading of Flag Bits for ROS Microcode Patching

IP.com Disclosure Number: IPCOM000047559D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Hughes, JE Oliver, BL [+details]

Abstract

In a ROS (read-only storage) patching scheme, it is desired that each micro-instruction in ROS have an associated flag bit stored in RAM (random-access memory). When a processor reads an instruction from ROS, that instruction's corresponding flag bit is also read. The flag bit being a logical "1" indicates that the instruction, or a sequence of instructions, has been modified and now resides in another designated portion of RAM. The problem that occurs in a ROS patching scheme such as this is how to load or alter the flag bits in RAM where the support processor having that task is not directly coupled to the system address bus. Referring to the figure, the flag bits are loaded into RAM 10 by the support processor 12 via the support bus interface (SBI) 14 and an address register 16.