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Deep Dielectric Isolation

IP.com Disclosure Number: IPCOM000047575D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Malaviya, SD [+details]

Abstract

A submicron size, deep trench isolation may be formed in the single crystal silicon according to the following process. 1. N+ subcollector 12, epitaxial layer 13, thin silicon dioxide layer 14 of about 10-nanometer thickness are formed in and on the P-substrate 10. 2. Photolithography and hardening techniques are used to deposit a hardened photoresist layer 8 in selected areas. 3. Plasma deposit silicon nitride layer 15 of about 400 to 500 nanometers over the entire silicon wafer. 4. Reactive ion etch (RIE) back to form silicon nitride stud at the location where deep trench isolation is desired, as seen in Fig. 1. Strip the photoresist layer 8. Reactive ion etch to remove the oxide layer 14 in all areas except under the silicon nitride stud. 5.