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Formation of Submicron Grooves in Silicon

IP.com Disclosure Number: IPCOM000047579D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Riseman, J [+details]

Abstract

This article describes methods for forming narrow, such as submicrometer, dimensioned mask openings on a semiconductor body. Two insulator materials having different etching characteristics are used. One method involves depositing a P+ doped polysilicon layer 10 upon a silicon substrate 12. Layer 14 of silicon nitride (Si3N4) and layer 15 of silicon dioxide (SiO2) are formed over layer 10. Then using lithography and etching techniques portions of layers 14, 15 are removed to produce the Fig. 1 structure. A Si3N4 sidewall 16 is grown by a blanket deposition followed by anisotropic reaction ion etching to form a 200- to 300-nanometer layer 18 of silicon dioxide, as seen in Fig. 2. The exposed silicon is thermally oxidized. The silicon nitride sidewall layer 16 is removed by either chemical or plasma etching, as shown in Fig.