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Low Leakage Complementary Transistor Switch Cell

IP.com Disclosure Number: IPCOM000047593D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Martin, BW Ritter, GA Rivadeniera, CG Sullivan, SC [+details]

Abstract

The described layout reduces cell leakage currents for improved switching speed. The Complementary Transistor Switch (CTS) cell consists of two cross-coupled half cells formed by a very dense, integrated PNP and NPN, as shown in Fig. 1. The PNP load device has a lateral structure that is very susceptible to the parasitic PNP that is formed with the p+ isolation (ISO) region. The leakage path, shown in Fig. 2, can greatly reduce the switching speed of the PNP load transistor. Fig. 3 depicts the layout of the present cell design. Since the load transistor action occurs between the two horizontal p+ diffusions, one would like to retain the gain of the intended PNP by not affecting the physical base length.