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B Clock Driver for Electronic Chip in Place Test

IP.com Disclosure Number: IPCOM000047604D
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Culican, EF Eaton, PL [+details]

Abstract

In extending Level Sensitive Scan design (LSSD) [1] to the chip boundaries (electronic chip in place test (ECIPT)), as described in [2], a custom 12 latch may be employed. The custom latch minimizes the overhead area on the chip. Since the 12 latch requires special drives, the B clock driver may be utilized. The block diagram for the B clock driver for ECIPT is illustrated in Fig. 1. Fig. 2 shows the driver circuit, and Fig. 3 shows the ECIPT 12 latch. Examining the latch, its threshold can be seen to be approximately 1.35 V. For proper latch function, the B signal must reach the latch threshold before the B input is allowed to change. Examining the circuit of the driver, its threshold is approximately 1.4 V. For the critical latch operation (B rising), the latch will set when B reaches 1.35 V but stage 4 (Fig.