Late Address Path
Original Publication Date: 1983-Dec-01
Included in the Prior Art Database: 2005-Feb-07
In large storages with relatively slow storage cells, such as one-device cells, the access time is reduced by fast buffers being integrated on the storage chip. Assuming that the bytes consist of n bits, then these buffers are divided into n groups of 2N bits each, each group being directly connected to one of the n output drivers. In the case of an x$n organization, these buffers permit data blocks of 2N$n cells to be read at the same time and their information to be stored. As the connection between buffer and output driver is subject to a very short delay, it may be sufficient for part of the addresses, say, 2, in the case of 4$n buffers, and 3, in the case of 8$n buffers, to be switched only shortly before the time at which the output data are specified to be valid.